Apparatus and method for using a well current source to effect a dynamic threshold voltage of a mos transistor

ABSTRACT

Deep submicron wells of MOS transistors, implemented over an ungrounded well, exhibit two modes of operation: a current sink mode and a current source mode. While operation as a current sink is well understood and successfully controlled, it is also necessary to control the current provided in the current source mode of the well. A Schottky diode is connected between the well and the gate, the Schottky diode having a smaller barrier height than that of the PN junction of the well-to-source. For an NMOS transistor, current flows through the PN junction when the gate is high. When the gate is low, current flows through the Schottky diode. This difference of current flow results in a difference in transistor threshold, thereby achieving a dynamic threshold voltage using the current from the well when operating at the current source mode.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of U.S. patent applicationSer. No. 11/533,332, filed on Sep. 19, 2006, and claims priority to U.S.Provisional Patent Application Ser. No. 61/006,306, filed on Jan. 4,2008, each of which is incorporated herein in its entirety by thisreference thereto.

BACKGROUND OF THE INVENTION

The invention relates to MOS transistors. More specifically, theinvention relates to improving drive-strength and leakage of deepsubmicron MOS transistors when the well becomes a current source.

DESCRIPTION OF THE PRIOR ART

The advantages of dynamically adjustable threshold voltage of metaloxide semiconductor (MOS) transistors with respect to enhancingdrive-current or reducing leakage current is known. U.S. Pat. No.7,224,205, assigned to a common assignee and incorporated herein in itsentirety by this reference, provides one such solution, where a diode isconnected in a forward bias mode that provides a current, controlled bythe transistor input, that modifies the voltage of the transistor'swell. This is performed in such a way that, when the transistor isrequired to supply current, it has a lower threshold voltage than normaland, therefore, increases its drive capability. In the off state, thetransistor's threshold is higher, leading to a better leakagecharacteristic. In actual implementations, the source of the wellvoltage modification is a forward-biased diode that delivers current tothe well from the gate. The well voltage is effectively clamped by thewell to a source PN junction diode. The series connection of forwardbiased diodes creates a voltage divider that modulates the well voltageaccording to the voltage applied to the gate. It is possible to designthis voltage divider to effect the desired changes in well voltage withvery little expenditure of current.

In actual implementations it was observed that a relatively high amountof current is sourced to a floating well from the transistor itsupports. While it is desired to keep the current in thevoltage-dividing diode stack low, on the order of 1 nA, it has beenfound in some instances that the well acts as a current source,supplying several nAs. This observed behavior is shown in FIG. 1. Belowthe voltage where the well-to-source PN junction acts as a clamp, i.e.the region marked as 110, at just about 650 mV, the well acts as acurrent source, i.e. the region marked as 120. This occurs because deepsub-micron transistors have extremely thin gate oxides, and extremelysteep doping gradients. Both of these factors lead to tunnel currentsfrom either the gate or the drain. If the well is not normally grounded,it assumes a voltage of roughly the source junction clamping voltage,i.e. 650 mV. This behavior of the well as a current source is anundesirable effect and should be controlled.

Ebina, in U.S. Pat. No. 6,521,948, suggests the use of a reverse biasedPN junction to effect a dynamic threshold. However, in the presence ofthe currents observed above, Ebina's approach is limited to cases wherethe well does not operate as a current source, or where its currents arenegligible. However, in a deep submicron implementation this is not bethe case and, therefore, Ebina would not be applicable.

It would therefore be advantageous to provide a solution that eithereliminates or makes use of the current provided by the well whenoperating in the current source mode.

SUMMARY OF THE INVENTION

Deep submicron wells of MOS transistors, implemented over an ungroundedwell, exhibit two modes of operation: a current sink mode and a currentsource mode. While operation as a current sink is well understood andsuccessfully controlled, it is also necessary to control the currentprovided in the current source mode of the well. A Schottky diode isconnected between the well and the gate, the Schottky diode having asmaller barrier height than that of the PN junction of thewell-to-source. For an NMOS transistor, current flows through the PNjunction when the gate is high. When the gate is low, current flowsthrough the Schottky diode. This difference of current flow results in adifference in transistor threshold, thereby achieving a dynamicthreshold voltage using the current from the well when operating at thecurrent source mode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a graph showing the behavior of the well of a transistor as acurrent sink and as a current source (prior art);

FIG. 2 is a schematic diagram of a control circuit using a Schottkydiode to take advantage of the current of the current source mode of thewell;

FIG. 3 is a graph comparing the characteristics of a Schottky diode andPN diode;

FIG. 4 is a schematic diagram illustrating the operation of anembodiment of the invention when the well in a current sink mode;

FIG. 5 is a schematic diagram illustrating the operation of anembodiment of the invention when the well in a current source mode;

FIG. 6 shows the layout of a transistor implemented in accordance withof an embodiment of the invention;

FIG. 7 is a flowchart showing the steps for creating a transistor inaccordance with an embodiment of the disclosed invention;

FIG. 8 is a flowchart showing the steps for creating a transistor inaccordance with an embodiment of the invention; and

FIG. 9 is a schematic diagram showing a leakage control circuit using aSchottky diode and a capacitor, according to an embodiment of theinvention.

DETAILED DESCRIPTION OF THE INVENTION

Deep submicron wells of MOS transistors, implemented over an ungroundedwell, exhibit two modes of operation: a current sink mode and a currentsource mode. While operation as a current sink is well understood andsuccessfully controlled, it is also necessary to control the currentprovided in the current source mode of the well. Accordingly, a Schottkydiode is connected between the well and the gate, the Schottky diodehaving a smaller barrier height than that of the PN junction of thewell-to-source. For a NMOS transistor, current flows through the PNjunction when the gate is high. When the gate is low, current flowsthrough the Schottky diode. This difference of current flow results in adifference in transistor threshold, thereby achieving a dynamicthreshold voltage using the current from the well when, the transistoroperates in the current source mode.

In an embodiment of the invention, the current supplied when the wellacts as a current source is controlled by using the gate to control thewell voltage. FIG. 2 is a schematic diagram showing control circuit 200that uses a Schottky diode 240 to take advantage of the current of thecurrent source 210 mode of the well 220. When the gate voltage is low,the Schottky diode 240 acts as a clamp, holding the well 240 one diodedrop above the low gate voltage. For the desired threshold modulation,the diode 240 has a lower turn-on voltage than the well-to-source PNjunction 230. This criterion is satisfied by the Schottky diode 240. Ina 90 nm CMOS embodiment, cobalt silicide is used as a conductanceenhancing layer. In one embodiment of the invention, CoSi₂ is used asone side of the Schottky diode 240. When the silicide is placed incontact with a P-well, the effective barrier height is approximately0.46 volts, compared to a PN junction 230 barrier of typically 0.8volts. This indicates that the well voltage may be modulated by about0.34 volts, which is sufficient to effect a useful change in VT. Thecharacteristics of the diode 240 and the PN junction 230 are shown inFIG. 3 by curves 310 and 320, respectively.

FIG. 4 is a schematic diagram that illustrates the operation of anembodiment of the invention when the well is in a current sink mode 400.When the gate voltage V_(GATE) is high, e.g., one volt, current flow isthrough the PN junction 230 formed by the well-to-source diode. Thisestablishes a relatively high voltage on the well, on the order of 0.5volts, based on the curves shown in FIG. 3. Because the Schottky diode240 that is between the gate and the well is reverse biased, there willbe relatively little current flow through that device, and what flowthere is tends to increase the well voltage because it adds to thecurrent supplied from the transistor, as represented by the internalcurrent source 210.

FIG. 5 is a schematic diagram illustrating the operation of anembodiment of the invention when the well is in a current source mode500. In this embodiment, where the gate voltage is low, the current fromthe transistor's internal current sources 210 tends to flow through theSchottky diode 240 because its turn-on voltage is much lower than thatof the PN junction diode. This pulls the well voltage down to about 0.2volts in the conditions described herein, based on the curves shown inFIG. 3. The difference in well 220 voltage creates a difference inthreshold voltage, so that there is more drive current available thanexpected from a fixed well voltage. Because the well is always at avoltage which is positive with respect to the source, a transistor ofthis should have a heavier than normal threshold voltage implant, e.g.,approximately 10¹³ ions/cm². Because the currents are small, it would beadvantageous in an embodiment of the invention to place a capacitancebetween the gate and the well. This capacitance enables the wellpotential to change rapidly, and enhances the transient drive capabilityof the transistor.

FIG. 6 illustrates a layout 600 of a transistor implemented inaccordance with an embodiment of the invention. Three active regions aremarked as 610, where the transistor is formed 620, where the diode 240is formed, and where a capacitor is formed 630. The Schottky diode 240is formed by eliminating P+ and N+ implants from its active region. WhenCoSi₂ is formed in that active region, without P+ or N+ doping, theresult is a Schottky diode. A metal line 640 contacts the gate 650 ofthe transistor, the Schottky diode 240, and the capacitor, forming theinput to the transistor. The metal lines 660 and 670 contact the sourceand drain regions of the transistor, respectively. The entire structureis formed in a well 680.

FIG. 7 is a flowchart 700 that shows the steps for creating a transistorin accordance with an embodiment of the invention. In step S710, an NMOStransistor is formed in a well, the MOS having a gate region, a drainregion, a source region, and a well region. In step S720, a Schottkydiode is formed with its anode coupled to the well and its cathodecoupled to the gate of the NMOS transistor. In step S720, a capacitor isformed between the gate and the well, essentially in parallel to theSchottky diode.

FIG. 8 shows a process flow implementing the transistor in accordancewith an embodiment of the invention. In steps S805-1, S805-2, andS805-3, the active areas of the transistor 610, the Schottky diode 620,and the capacitor are formed, respectively. In step S810, a commonisolated well 680 is formed. In steps S815-1 and S815-3, an implant isperformed to set the threshold voltage for the transistor and thecapacitor, respectively. The transistor can be implemented without thecapacitor, as discussed above. In step S820, polysilicon, also referredto as poly, is deposited on the entire area. In steps S825-1, S825-2,and S825-3, an etch is performed to remove polysilicon and thus form thegate 650, to clear over the Schottky diode, and to form the capacitorelectrode respectively. In step S830-1, pocket and lightly doped drain(LDD) implants are made. In step S835, spacers are formed on thepolysilicon and unprotected gate oxide is removed. In step S840-1,implant of the transistor's source, drain, and gate takes place; whilein step S840-3, the implant of the capacitor poly takes place. In stepS845, silicide is formed on the source and the drain of the transistor,over the Shottcky region and over the poly of the capacitor. In stepS850, protection of all structures is performed by applying aninter-layer dielectric. In step S855, contacts 690 to all structures areformed.

FIG. 9 is a schematic diagram of the leakage control circuit 900according to the embodiment of the invention. The NMOS transistor 910 isconnected to a Schottky diode 920 such that the diode's anode terminalis coupled to the well of the NMOS transistor 910, and the cathodeterminal of the diode is coupled to the gate of the NMOS transistor 910.A capacitor 930 is connected in parallel with the Schottky diode 920with one terminal connected to the anode of the Schottky diode 920 andthe other terminal connected to the cathode of the Schottky diode 920.The schematic of FIG. 9 corresponds to the layout shown in FIG. 6.

A person skilled in the art would readily note that the descriptionsherein where described with respect to a NMOS transistor. Such a personwould further realize that it is straightforward to adapt the teachingsherein for the purpose of PMOS transistors, with the applicable changesrequired due to the different polarity of the PMOS transistor. The samematerial CoSi₂ also creates a useful Schottky diode with N-type silicon.In this case, the nominal barrier is somewhat higher, i.e. 0.64 volts,but can be reduced by controlling the well doping. It is thereforeapparent that the well voltage can be modulated by at least 200 mV,which is sufficient to effect useful VT modulation. Other materials,such as NiSi₂, may be used to act as a conductivity enhancing layer.Such material is also a useful Schottky barrier diode material, bothwith respect to a P-well and with respect to an N-well. Shottky diodesusing different silicides may be provided on the same integrated circuit(IC). It would be further noted by an artisan that the principles of theinvention disclosed hereinabove are applicable to both bulk MOSimplementations, as well as various types of semiconductor overinsulator (SOI) implementations, without departing from the teachingsherein.

Accordingly, although the invention has been described in detail withreference to a particular preferred embodiment, persons possessingordinary skill in the art to which this invention pertains willappreciate that various modifications and enhancements may be madewithout departing from the spirit and scope of the claims that follow.

1. An apparatus, comprising: a MOS transistor having a source terminal,a drain terminal, a gate terminal and a well terminal; and a controldiode coupled between said source terminal and said gate terminal, saidcontrol diode constructed to provide a barrier voltage that issufficiently below a barrier voltage of a diode formed between said wellof said MOS transistor and said source of said MOS transistor, to effecta dynamic threshold voltage control; wherein said circuit is soconstructed that said control diode is forward biased when said gatevoltage is approximately equal to said source voltage, and wherein saidcontrol diode is constructed to act as a clamp that holds said well atone diode voltage drop above a low gate voltage.
 2. The apparatus ofclaim 1, said MOS transistor comprising: a first active area of a firstconductivity type formed in said well; and a gate formed over said firstactive area to define of a drain region and a source region.
 3. Theapparatus of claim 1, wherein said control diode comprises a Schottkydiode.
 4. The apparatus of claim 3, said Schottky diode comprising: asecond active area of a first conductivity type formed in said well; anda metal contact formed with respect to said second active area.
 5. Theapparatus of claim 3, wherein one side of said Schottky diode is formedof a silicide.
 6. The apparatus of claim 5, wherein said silicidecomprises one of CoSi₂ and NiSi₂.
 7. The apparatus of claim 1, furthercomprising: a capacitor coupled between said well of said MOS transistorand said gate of said MOS transistor and constructed to exhibit any ofthe properties of changing said well potential rapidly and enhancingtransient drive capability of said MOS transistor.
 8. The apparatus ofclaim 7, said capacitor further comprising: a third active area of afirst conductivity type formed in said well; and a polysilicon areaformed over said third active area.
 9. The apparatus of claim 1, whereinsaid MOS transistor comprises one of an NMOS transistor and a PMOStransistor.
 10. An integrated circuit comprising at least one said NMOStransistor of claim 9 and at least one said PMOS transistor of claim 9,wherein said control diode of said at least NMOS transistor isconstructed of a first silicide type and wherein said control diode ofsaid at least PMOS transistor is constructed of a second silicide type.11. A method for manufacturing a semiconductor, comprising the steps of:forming a well in a substrate; forming an MOS transistor in said well,said MOS transistor comprising a source region, a drain region, and agate, said MOS transistor formed to operate at a predetermined thresholdvoltage; and forming a control diode coupled between said gate and saidwell, said control diode formed to have a barrier voltage that issufficiently below a barrier voltage of a diode formed between said welland said source to effect a change of said threshold voltage, whereinsaid control diode is so formed that it is forward biased when said gatevoltage is approximately equal to said source voltage, and wherein saidcontrol diode is formed to act as a clamp that holds said well at onediode voltage drop above a low gate voltage; wherein said MOS transistoris configured for dynamic threshold voltage control.
 12. The method ofclaim 11, said step of forming said MOS transistor further comprisingthe steps of: forming a first active area of a first conductivity typein said well; and forming a gate over said first active area.
 13. Themethod of claim 11, wherein said control diode comprises a Schottkydiode.
 14. The method of claim 13, said step of wherein forming saidcontrol diode further comprising the step of: forming a second activearea of a first conductivity type in said well; and forming a metalcontact with respect to said second active area.
 15. The method of claim13, further comprising the step of: forming one side of said Schottkydiode with a silicide.
 16. The method of claim 14, wherein said silicidecomprises one of CoSi₂ and NiSi₂.
 17. The method of claim 11, furthercomprising the step of: forming a capacitor coupled between said welland said gate to exhibit any of the properties of changing said wellpotential rapidly and enhancing transient drive capability of said MOStransistor.
 18. The method of claim 16, said step of forming a capacitorfurther comprising the steps of: forming a third active area of a firstconductivity type in said well; and forming a polysilicon area over saidthird active area.
 19. The method of claim 11, wherein said MOStransistor comprises one of an NMOS transistor and a PMOS transistor.20. The method of claim 18, further comprising the steps of: formingsaid control diode of said NMOS transistor from a first silicide type;and forming said control diode of said PMOS transistor from a secondsilicide type.
 21. The method of claim 11, said step of forming a well,a MOS transistor, and a control diode comprising the steps of: formingactive regions for said MOS transistor and said control diode in saidsubstrate; forming a common isolated well; implanting said MOStransistor to set a threshold voltage; depositing polysilicon on atleast said common isolated well; etching said polysilicon from said gateand said control diode; performing pocket and lightly doped drain (LDD)implants to said MOS transistor; forming spacers on polysilicon;clearing unprotected gate oxide from said gate; implanting said source,said drain, and said gate; and forming silicide on said source, saiddrain, and said control diode; protecting said MOS transistor and saidcontrol diode by an inter-layer dielectric; and forming contacts to saidsource, said drain, said gate, and said control diode.
 22. The method ofclaim 20, further comprising the steps of: forming an active region fora capacitor; implanting said capacitor to set a threshold voltage;etching polysilicon from said capacitor to form a capacitor electrode;implanting said capacitor polysilicon; forming silicide on saidcapacitor polysilicon; and protecting said capacitor with an inter-layerdielectric.
 23. A method of manufacturing a semiconductor device,comprising the steps of: forming active regions for a MOS transistor anda Schottcky diode in a substrate; forming a common isolated well;implanting said MOS transistor to set a threshold voltage; depositingpolysilicon on at least said common isolated well; etching saidpolysilicon from said gate and said Schottky diode; performing pocketand lightly doped drain (LDD) implants to said MOS transistor; formingspacers on polysilicon; clearing unprotected gate oxide from said gate;implanting said source, said drain, and said gate; forming silicide onsaid source, said drain, and said Schottky diode; protecting said MOStransistor and said Schottky diode with an inter-layer dielectric; andforming contacts to said source, said drain, said gate, and saidSchottky diode; forming said Schottky diode to have a barrier voltagethat is sufficiently below a barrier voltage of a diode formed betweensaid well and said source to effect a change of said threshold voltage,wherein said Schottky diode is forward biased when said gate voltage isapproximately equal to said source voltage, and wherein said Schottkydiode is formed to act as a clamp to hold said well at one diode voltagedrop above a low gate voltage; wherein said MOS transistor providesdynamic threshold voltage control.
 24. The method of claim 21, furthercomprising the steps of: forming an active region for a capacitor;implanting said capacitor to set a threshold voltage; etchingpolysilicon from said capacitor to form a capacitor electrode;implanting said capacitor polysilicon; forming silicide on saidcapacitor polysilicon; and protecting said capacitor with an inter-layerdielectric.